Semiconductor Engineering

Non-Traditional Design of Dynamic Logic Gates and Circuits with FDSOI FETs

A new technical paper titled “Non-Traditional Design of Dynamic Logics using FDSOI for Ultra-Efficient Computing” was published by researchers at University of Stuttgart, UC Berkeley, Indian Institute ...
EDN

Power dissipation in portables: Design considerations using low-power CMOS ICs

When a CMOS circuit is in an idle state there is still some static power dissipation–a result of leakage current through nominally off transistors. Both nMOS and pMOS transistors used in CMOS logic ...
EDN

Driving CMOS totem poles with logic signals, AC coupling, and grounded gates

Despite massive, large-scale integration being ubiquitous in contemporary electronic design, discrete MOSFETs in the classic CMOS totem pole topology are still sometimes indispensable. This makes tips ...
Semiconductor Engineering

NAND and NOR logic-in-memory comprising silicon nanowire feedback field-effect transistors

“The processing of large amounts of data requires a high energy efficiency and fast processing time for high-performance computing systems. However, conventional von Neumann computing systems have ...
Design News

What Should We Do With the Inputs to Unused Logic Gates & Functions? (Part 1)

I fear the topic of this column is poised to unleash a tsunami of controversy. My engineering accomplice Joe Farr says that this is one of those topics that, when presented to 10 different engineers, ...